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<a href="#nested-classes">Data Structures</a> &#124;
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<div class="title">Qspipsu_v1_0</div>  </div>
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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_qspi_psu___msg.html">XQspiPsu_Msg</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef contains configuration information for a flash message.  <a href="struct_x_qspi_psu___msg.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_qspi_psu___config.html">XQspiPsu_Config</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef contains configuration information for the device.  <a href="struct_x_qspi_psu___config.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">The <a class="el" href="struct_x_qspi_psu.html" title="The XQspiPsu driver instance data. ">XQspiPsu</a> driver instance data.  <a href="struct_x_qspi_psu.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ga49734e127e6359b15c1ce7f117748c36"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga49734e127e6359b15c1ce7f117748c36">XQSPIPS_BASEADDR</a>&#160;&#160;&#160;0XFF0F0000U</td></tr>
<tr class="memdesc:ga49734e127e6359b15c1ce7f117748c36"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI Base Address.  <a href="#ga49734e127e6359b15c1ce7f117748c36">More...</a><br /></td></tr>
<tr class="separator:ga49734e127e6359b15c1ce7f117748c36"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga137198cf9ed99131ff88af7201399ebe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga137198cf9ed99131ff88af7201399ebe">XQSPIPSU_BASEADDR</a>&#160;&#160;&#160;0xFF0F0100U</td></tr>
<tr class="memdesc:ga137198cf9ed99131ff88af7201399ebe"><td class="mdescLeft">&#160;</td><td class="mdescRight">GQSPI Base Address.  <a href="#ga137198cf9ed99131ff88af7201399ebe">More...</a><br /></td></tr>
<tr class="separator:ga137198cf9ed99131ff88af7201399ebe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab5bb698f82719c1ffdf5055dd5ebf939"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gab5bb698f82719c1ffdf5055dd5ebf939">XQSPIPS_EN_REG</a>&#160;&#160;&#160;( ( <a class="el" href="group__qspipsu__v1__0.html#ga49734e127e6359b15c1ce7f117748c36">XQSPIPS_BASEADDR</a> ) + 0X00000014U )</td></tr>
<tr class="memdesc:gab5bb698f82719c1ffdf5055dd5ebf939"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPS_EN_REG.  <a href="#gab5bb698f82719c1ffdf5055dd5ebf939">More...</a><br /></td></tr>
<tr class="separator:gab5bb698f82719c1ffdf5055dd5ebf939"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1d76a2f706f3988da79345132e484303"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga1d76a2f706f3988da79345132e484303">XQSPIPSU_CFG_OFFSET</a>&#160;&#160;&#160;0X00000000U</td></tr>
<tr class="memdesc:ga1d76a2f706f3988da79345132e484303"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_CFG.  <a href="#ga1d76a2f706f3988da79345132e484303">More...</a><br /></td></tr>
<tr class="separator:ga1d76a2f706f3988da79345132e484303"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga02a2df38913ec3616e70351637cbbb50"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga02a2df38913ec3616e70351637cbbb50">XQSPIPSU_LQSPI_CR_OFFSET</a>&#160;&#160;&#160;0X000000A0U</td></tr>
<tr class="memdesc:ga02a2df38913ec3616e70351637cbbb50"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_CFG.  <a href="#ga02a2df38913ec3616e70351637cbbb50">More...</a><br /></td></tr>
<tr class="separator:ga02a2df38913ec3616e70351637cbbb50"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga02a2df38913ec3616e70351637cbbb50"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga02a2df38913ec3616e70351637cbbb50">XQSPIPSU_LQSPI_CR_OFFSET</a>&#160;&#160;&#160;0X000000A0U</td></tr>
<tr class="memdesc:ga02a2df38913ec3616e70351637cbbb50"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_CFG.  <a href="#ga02a2df38913ec3616e70351637cbbb50">More...</a><br /></td></tr>
<tr class="separator:ga02a2df38913ec3616e70351637cbbb50"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac5bfff58ddca187becec7c533cf355fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gac5bfff58ddca187becec7c533cf355fe">XQSPIPSU_LQSPI_CR_LINEAR_MASK</a>&#160;&#160;&#160;0x80000000</td></tr>
<tr class="memdesc:gac5bfff58ddca187becec7c533cf355fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">LQSPI mode enable.  <a href="#gac5bfff58ddca187becec7c533cf355fe">More...</a><br /></td></tr>
<tr class="separator:gac5bfff58ddca187becec7c533cf355fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6fbc52b88d443b2a5ea258ff83ef71f2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga6fbc52b88d443b2a5ea258ff83ef71f2">XQSPIPSU_LQSPI_CR_TWO_MEM_MASK</a>&#160;&#160;&#160;0x40000000</td></tr>
<tr class="memdesc:ga6fbc52b88d443b2a5ea258ff83ef71f2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Both memories or one.  <a href="#ga6fbc52b88d443b2a5ea258ff83ef71f2">More...</a><br /></td></tr>
<tr class="separator:ga6fbc52b88d443b2a5ea258ff83ef71f2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga66a4736f3e48910c8ba8dc2999b16558"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga66a4736f3e48910c8ba8dc2999b16558">XQSPIPSU_LQSPI_CR_SEP_BUS_MASK</a>&#160;&#160;&#160;0x20000000</td></tr>
<tr class="memdesc:ga66a4736f3e48910c8ba8dc2999b16558"><td class="mdescLeft">&#160;</td><td class="mdescRight">Seperate memory bus.  <a href="#ga66a4736f3e48910c8ba8dc2999b16558">More...</a><br /></td></tr>
<tr class="separator:ga66a4736f3e48910c8ba8dc2999b16558"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa7502d70b7ddd899d5bf8bba3f23d70e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gaa7502d70b7ddd899d5bf8bba3f23d70e">XQSPIPSU_LQSPI_CR_U_PAGE_MASK</a>&#160;&#160;&#160;0x10000000</td></tr>
<tr class="memdesc:gaa7502d70b7ddd899d5bf8bba3f23d70e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Upper memory page.  <a href="#gaa7502d70b7ddd899d5bf8bba3f23d70e">More...</a><br /></td></tr>
<tr class="separator:gaa7502d70b7ddd899d5bf8bba3f23d70e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5406192835c4f1d618b56626790628b1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga5406192835c4f1d618b56626790628b1">XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK</a>&#160;&#160;&#160;0x01000000</td></tr>
<tr class="memdesc:ga5406192835c4f1d618b56626790628b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Upper memory page.  <a href="#ga5406192835c4f1d618b56626790628b1">More...</a><br /></td></tr>
<tr class="separator:ga5406192835c4f1d618b56626790628b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0eecbc04289c520b605393012c8715ff"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga0eecbc04289c520b605393012c8715ff">XQSPIPSU_LQSPI_CR_MODE_EN_MASK</a>&#160;&#160;&#160;0x02000000</td></tr>
<tr class="memdesc:ga0eecbc04289c520b605393012c8715ff"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable mode bits.  <a href="#ga0eecbc04289c520b605393012c8715ff">More...</a><br /></td></tr>
<tr class="separator:ga0eecbc04289c520b605393012c8715ff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga40238108ef1f0763edaf8adc59c03d72"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga40238108ef1f0763edaf8adc59c03d72">XQSPIPSU_LQSPI_CR_MODE_ON_MASK</a>&#160;&#160;&#160;0x01000000</td></tr>
<tr class="memdesc:ga40238108ef1f0763edaf8adc59c03d72"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mode on.  <a href="#ga40238108ef1f0763edaf8adc59c03d72">More...</a><br /></td></tr>
<tr class="separator:ga40238108ef1f0763edaf8adc59c03d72"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad3cd6ea3b67401b777b26365937e9c97"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gad3cd6ea3b67401b777b26365937e9c97">XQSPIPSU_LQSPI_CR_MODE_BITS_MASK</a>&#160;&#160;&#160;0x00FF0000</td></tr>
<tr class="memdesc:gad3cd6ea3b67401b777b26365937e9c97"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mode value for dual I/O or quad I/O.  <a href="#gad3cd6ea3b67401b777b26365937e9c97">More...</a><br /></td></tr>
<tr class="separator:gad3cd6ea3b67401b777b26365937e9c97"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad327ae631cb6e447615bc9534738af72"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gad327ae631cb6e447615bc9534738af72">XQSPIPS_LQSPI_CR_INST_MASK</a>&#160;&#160;&#160;0x000000FF</td></tr>
<tr class="memdesc:gad327ae631cb6e447615bc9534738af72"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read instr code.  <a href="#gad327ae631cb6e447615bc9534738af72">More...</a><br /></td></tr>
<tr class="separator:gad327ae631cb6e447615bc9534738af72"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6f187c067994aa193d43051cb5fef0db"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga6f187c067994aa193d43051cb5fef0db">XQSPIPS_LQSPI_CR_RST_STATE</a>&#160;&#160;&#160;0x80000003</td></tr>
<tr class="memdesc:ga6f187c067994aa193d43051cb5fef0db"><td class="mdescLeft">&#160;</td><td class="mdescRight">Default LQSPI CR value.  <a href="#ga6f187c067994aa193d43051cb5fef0db">More...</a><br /></td></tr>
<tr class="separator:ga6f187c067994aa193d43051cb5fef0db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3c05a7421b8aea31df3d026189282cce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga3c05a7421b8aea31df3d026189282cce">XQSPIPS_LQSPI_CFG_RST_STATE</a>&#160;&#160;&#160;0x800238C1</td></tr>
<tr class="memdesc:ga3c05a7421b8aea31df3d026189282cce"><td class="mdescLeft">&#160;</td><td class="mdescRight">Default LQSPI CFG value.  <a href="#ga3c05a7421b8aea31df3d026189282cce">More...</a><br /></td></tr>
<tr class="separator:ga3c05a7421b8aea31df3d026189282cce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadae24d033fb12577e3e4eda5427a950a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gadae24d033fb12577e3e4eda5427a950a">XQSPIPSU_ISR_OFFSET</a>&#160;&#160;&#160;0X00000004U</td></tr>
<tr class="memdesc:gadae24d033fb12577e3e4eda5427a950a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_ISR.  <a href="#gadae24d033fb12577e3e4eda5427a950a">More...</a><br /></td></tr>
<tr class="separator:gadae24d033fb12577e3e4eda5427a950a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab8e3a4621239cb556fc8acdd0a6d10b6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gab8e3a4621239cb556fc8acdd0a6d10b6">XQSPIPSU_IER_OFFSET</a>&#160;&#160;&#160;0X00000008U</td></tr>
<tr class="memdesc:gab8e3a4621239cb556fc8acdd0a6d10b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_IER.  <a href="#gab8e3a4621239cb556fc8acdd0a6d10b6">More...</a><br /></td></tr>
<tr class="separator:gab8e3a4621239cb556fc8acdd0a6d10b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5eb684785dfb0a249b18126089624b91"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga5eb684785dfb0a249b18126089624b91">XQSPIPSU_IDR_OFFSET</a>&#160;&#160;&#160;0X0000000CU</td></tr>
<tr class="memdesc:ga5eb684785dfb0a249b18126089624b91"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_IDR.  <a href="#ga5eb684785dfb0a249b18126089624b91">More...</a><br /></td></tr>
<tr class="separator:ga5eb684785dfb0a249b18126089624b91"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1711ff533a11dd37b3d72056050025e5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga1711ff533a11dd37b3d72056050025e5">XQSPIPSU_IMR_OFFSET</a>&#160;&#160;&#160;0X00000010U</td></tr>
<tr class="memdesc:ga1711ff533a11dd37b3d72056050025e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_IMR.  <a href="#ga1711ff533a11dd37b3d72056050025e5">More...</a><br /></td></tr>
<tr class="separator:ga1711ff533a11dd37b3d72056050025e5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5b7b95790bfeb5bfb3dfd63e4a5e76cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga5b7b95790bfeb5bfb3dfd63e4a5e76cc">XQSPIPSU_EN_OFFSET</a>&#160;&#160;&#160;0X00000014U</td></tr>
<tr class="memdesc:ga5b7b95790bfeb5bfb3dfd63e4a5e76cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_EN_REG.  <a href="#ga5b7b95790bfeb5bfb3dfd63e4a5e76cc">More...</a><br /></td></tr>
<tr class="separator:ga5b7b95790bfeb5bfb3dfd63e4a5e76cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4884f0160746c6696598ef6dda1fc9ff"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga4884f0160746c6696598ef6dda1fc9ff">XQSPIPSU_TXD_OFFSET</a>&#160;&#160;&#160;0X0000001CU</td></tr>
<tr class="memdesc:ga4884f0160746c6696598ef6dda1fc9ff"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_TXD.  <a href="#ga4884f0160746c6696598ef6dda1fc9ff">More...</a><br /></td></tr>
<tr class="separator:ga4884f0160746c6696598ef6dda1fc9ff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga68b0b4316693414546980dea7baaf0a4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga68b0b4316693414546980dea7baaf0a4">XQSPIPSU_RXD_OFFSET</a>&#160;&#160;&#160;0X00000020U</td></tr>
<tr class="memdesc:ga68b0b4316693414546980dea7baaf0a4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_RXD.  <a href="#ga68b0b4316693414546980dea7baaf0a4">More...</a><br /></td></tr>
<tr class="separator:ga68b0b4316693414546980dea7baaf0a4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga33bc760357127168b3a665f969036421"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga33bc760357127168b3a665f969036421">XQSPIPSU_TX_THRESHOLD_OFFSET</a>&#160;&#160;&#160;0X00000028U</td></tr>
<tr class="memdesc:ga33bc760357127168b3a665f969036421"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_TX_THRESHOLD.  <a href="#ga33bc760357127168b3a665f969036421">More...</a><br /></td></tr>
<tr class="separator:ga33bc760357127168b3a665f969036421"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga97be55c27b71a154877fb5f919d627f1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga97be55c27b71a154877fb5f919d627f1">XQSPIPSU_RX_THRESHOLD_OFFSET</a>&#160;&#160;&#160;0X0000002CU</td></tr>
<tr class="memdesc:ga97be55c27b71a154877fb5f919d627f1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_RX_THRESHOLD.  <a href="#ga97be55c27b71a154877fb5f919d627f1">More...</a><br /></td></tr>
<tr class="separator:ga97be55c27b71a154877fb5f919d627f1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad50a54ee932051b2fed093ef6f2e8a12"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gad50a54ee932051b2fed093ef6f2e8a12">XQSPIPSU_GPIO_OFFSET</a>&#160;&#160;&#160;0X00000030U</td></tr>
<tr class="memdesc:gad50a54ee932051b2fed093ef6f2e8a12"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_GPIO.  <a href="#gad50a54ee932051b2fed093ef6f2e8a12">More...</a><br /></td></tr>
<tr class="separator:gad50a54ee932051b2fed093ef6f2e8a12"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4636d144794bb35424cacd6f6d49781a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga4636d144794bb35424cacd6f6d49781a">XQSPIPSU_LPBK_DLY_ADJ_OFFSET</a>&#160;&#160;&#160;0X00000038U</td></tr>
<tr class="memdesc:ga4636d144794bb35424cacd6f6d49781a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_LPBK_DLY_ADJ.  <a href="#ga4636d144794bb35424cacd6f6d49781a">More...</a><br /></td></tr>
<tr class="separator:ga4636d144794bb35424cacd6f6d49781a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3bfe2023b6a6ce56e9d13f130bd1c86d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga3bfe2023b6a6ce56e9d13f130bd1c86d">XQSPIPSU_GEN_FIFO_OFFSET</a>&#160;&#160;&#160;0X00000040U</td></tr>
<tr class="memdesc:ga3bfe2023b6a6ce56e9d13f130bd1c86d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_GEN_FIFO.  <a href="#ga3bfe2023b6a6ce56e9d13f130bd1c86d">More...</a><br /></td></tr>
<tr class="separator:ga3bfe2023b6a6ce56e9d13f130bd1c86d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga84156abbc51d17b988b1e82c584be10d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga84156abbc51d17b988b1e82c584be10d">XQSPIPSU_SEL_OFFSET</a>&#160;&#160;&#160;0X00000044U</td></tr>
<tr class="memdesc:ga84156abbc51d17b988b1e82c584be10d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_SEL.  <a href="#ga84156abbc51d17b988b1e82c584be10d">More...</a><br /></td></tr>
<tr class="separator:ga84156abbc51d17b988b1e82c584be10d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac14f429fa7d15b5c4bf2808ed08e7120"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gac14f429fa7d15b5c4bf2808ed08e7120">XQSPIPSU_FIFO_CTRL_OFFSET</a>&#160;&#160;&#160;0X0000004CU</td></tr>
<tr class="memdesc:gac14f429fa7d15b5c4bf2808ed08e7120"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_FIFO_CTRL.  <a href="#gac14f429fa7d15b5c4bf2808ed08e7120">More...</a><br /></td></tr>
<tr class="separator:gac14f429fa7d15b5c4bf2808ed08e7120"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5a8034417fd3c9846c968679c1cad859"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga5a8034417fd3c9846c968679c1cad859">XQSPIPSU_GF_THRESHOLD_OFFSET</a>&#160;&#160;&#160;0X00000050U</td></tr>
<tr class="memdesc:ga5a8034417fd3c9846c968679c1cad859"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_GF_THRESHOLD.  <a href="#ga5a8034417fd3c9846c968679c1cad859">More...</a><br /></td></tr>
<tr class="separator:ga5a8034417fd3c9846c968679c1cad859"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf657fc3a38e22e512c0f7cf03bda1ad7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gaf657fc3a38e22e512c0f7cf03bda1ad7">XQSPIPSU_POLL_CFG_OFFSET</a>&#160;&#160;&#160;0X00000054U</td></tr>
<tr class="memdesc:gaf657fc3a38e22e512c0f7cf03bda1ad7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_POLL_CFG.  <a href="#gaf657fc3a38e22e512c0f7cf03bda1ad7">More...</a><br /></td></tr>
<tr class="separator:gaf657fc3a38e22e512c0f7cf03bda1ad7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga311de6f25e5cf64057e9ba429cf86507"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga311de6f25e5cf64057e9ba429cf86507">XQSPIPSU_P_TO_OFFSET</a>&#160;&#160;&#160;0X00000058U</td></tr>
<tr class="memdesc:ga311de6f25e5cf64057e9ba429cf86507"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_P_TIMEOUT.  <a href="#ga311de6f25e5cf64057e9ba429cf86507">More...</a><br /></td></tr>
<tr class="separator:ga311de6f25e5cf64057e9ba429cf86507"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4951a0b7d9ce35780f74864a196092e4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga4951a0b7d9ce35780f74864a196092e4">XQSPIPSU_XFER_STS_OFFSET</a>&#160;&#160;&#160;0X0000005CU</td></tr>
<tr class="memdesc:ga4951a0b7d9ce35780f74864a196092e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_XFER_STS.  <a href="#ga4951a0b7d9ce35780f74864a196092e4">More...</a><br /></td></tr>
<tr class="separator:ga4951a0b7d9ce35780f74864a196092e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadda8c30c269feb26bc40f588da2c6097"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gadda8c30c269feb26bc40f588da2c6097">XQSPIPSU_GF_SNAPSHOT_OFFSET</a>&#160;&#160;&#160;0X00000060U</td></tr>
<tr class="memdesc:gadda8c30c269feb26bc40f588da2c6097"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_GF_SNAPSHOT.  <a href="#gadda8c30c269feb26bc40f588da2c6097">More...</a><br /></td></tr>
<tr class="separator:gadda8c30c269feb26bc40f588da2c6097"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga419ba63e8028ea7e8aa833523ea3a785"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga419ba63e8028ea7e8aa833523ea3a785">XQSPIPSU_RX_COPY_OFFSET</a>&#160;&#160;&#160;0X00000064U</td></tr>
<tr class="memdesc:ga419ba63e8028ea7e8aa833523ea3a785"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_RX_COPY.  <a href="#ga419ba63e8028ea7e8aa833523ea3a785">More...</a><br /></td></tr>
<tr class="separator:ga419ba63e8028ea7e8aa833523ea3a785"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9dae139fcca838438b3e14f4306f1f06"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga9dae139fcca838438b3e14f4306f1f06">XQSPIPSU_MOD_ID_OFFSET</a>&#160;&#160;&#160;0X000000FCU</td></tr>
<tr class="memdesc:ga9dae139fcca838438b3e14f4306f1f06"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_MOD_ID.  <a href="#ga9dae139fcca838438b3e14f4306f1f06">More...</a><br /></td></tr>
<tr class="separator:ga9dae139fcca838438b3e14f4306f1f06"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3b9c82ef758ea9e8bfda707130051091"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga3b9c82ef758ea9e8bfda707130051091">XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET</a>&#160;&#160;&#160;0X00000700U</td></tr>
<tr class="memdesc:ga3b9c82ef758ea9e8bfda707130051091"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_QSPIDMA_DST_ADDR.  <a href="#ga3b9c82ef758ea9e8bfda707130051091">More...</a><br /></td></tr>
<tr class="separator:ga3b9c82ef758ea9e8bfda707130051091"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab2dea188a0404d6e555c4ff2839eb86a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gab2dea188a0404d6e555c4ff2839eb86a">XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET</a>&#160;&#160;&#160;0X00000704U</td></tr>
<tr class="memdesc:gab2dea188a0404d6e555c4ff2839eb86a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_QSPIDMA_DST_SIZE.  <a href="#gab2dea188a0404d6e555c4ff2839eb86a">More...</a><br /></td></tr>
<tr class="separator:gab2dea188a0404d6e555c4ff2839eb86a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8fd8100c320c3da46a93af5adf6592f0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga8fd8100c320c3da46a93af5adf6592f0">XQSPIPSU_QSPIDMA_DST_STS_OFFSET</a>&#160;&#160;&#160;0X00000708U</td></tr>
<tr class="memdesc:ga8fd8100c320c3da46a93af5adf6592f0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_QSPIDMA_DST_STS.  <a href="#ga8fd8100c320c3da46a93af5adf6592f0">More...</a><br /></td></tr>
<tr class="separator:ga8fd8100c320c3da46a93af5adf6592f0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1c49b7d688c394b3bb37d4293fa34df5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga1c49b7d688c394b3bb37d4293fa34df5">XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET</a>&#160;&#160;&#160;0X0000070CU</td></tr>
<tr class="memdesc:ga1c49b7d688c394b3bb37d4293fa34df5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_QSPIDMA_DST_CTRL.  <a href="#ga1c49b7d688c394b3bb37d4293fa34df5">More...</a><br /></td></tr>
<tr class="separator:ga1c49b7d688c394b3bb37d4293fa34df5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7fcb2a02499c783baa52e6dbba23e228"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga7fcb2a02499c783baa52e6dbba23e228">XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET</a>&#160;&#160;&#160;0X00000714U</td></tr>
<tr class="memdesc:ga7fcb2a02499c783baa52e6dbba23e228"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_QSPIDMA_DST_I_STS.  <a href="#ga7fcb2a02499c783baa52e6dbba23e228">More...</a><br /></td></tr>
<tr class="separator:ga7fcb2a02499c783baa52e6dbba23e228"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaceea2425458ac2a40305f93e496865a9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gaceea2425458ac2a40305f93e496865a9">XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET</a>&#160;&#160;&#160;0X00000718U</td></tr>
<tr class="memdesc:gaceea2425458ac2a40305f93e496865a9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_QSPIDMA_DST_I_EN.  <a href="#gaceea2425458ac2a40305f93e496865a9">More...</a><br /></td></tr>
<tr class="separator:gaceea2425458ac2a40305f93e496865a9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga04b009825df34055ec8a92ac44e651fa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga04b009825df34055ec8a92ac44e651fa">XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET</a>&#160;&#160;&#160;0X0000071CU</td></tr>
<tr class="memdesc:ga04b009825df34055ec8a92ac44e651fa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_QSPIDMA_DST_I_DIS.  <a href="#ga04b009825df34055ec8a92ac44e651fa">More...</a><br /></td></tr>
<tr class="separator:ga04b009825df34055ec8a92ac44e651fa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga30ca967a9288020ef44470e6f09c2b6b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga30ca967a9288020ef44470e6f09c2b6b">XQSPIPSU_QSPIDMA_DST_IMR_OFFSET</a>&#160;&#160;&#160;0X00000720U</td></tr>
<tr class="memdesc:ga30ca967a9288020ef44470e6f09c2b6b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_QSPIDMA_DST_IMR.  <a href="#ga30ca967a9288020ef44470e6f09c2b6b">More...</a><br /></td></tr>
<tr class="separator:ga30ca967a9288020ef44470e6f09c2b6b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad11e1e53c55440afa41685846b74c9c7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gad11e1e53c55440afa41685846b74c9c7">XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET</a>&#160;&#160;&#160;0X00000724U</td></tr>
<tr class="memdesc:gad11e1e53c55440afa41685846b74c9c7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_QSPIDMA_DST_CTRL2.  <a href="#gad11e1e53c55440afa41685846b74c9c7">More...</a><br /></td></tr>
<tr class="separator:gad11e1e53c55440afa41685846b74c9c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga39b0151b1cd09cb2da8d67efeb8ec0cb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga39b0151b1cd09cb2da8d67efeb8ec0cb">XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET</a>&#160;&#160;&#160;0X00000728U</td></tr>
<tr class="memdesc:ga39b0151b1cd09cb2da8d67efeb8ec0cb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_QSPIDMA_DST_ADDR_MSB.  <a href="#ga39b0151b1cd09cb2da8d67efeb8ec0cb">More...</a><br /></td></tr>
<tr class="separator:ga39b0151b1cd09cb2da8d67efeb8ec0cb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4332dd0868d1843ae3a49d74844d2a8f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga4332dd0868d1843ae3a49d74844d2a8f">XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET</a>&#160;&#160;&#160;0X00000EFCU</td></tr>
<tr class="memdesc:ga4332dd0868d1843ae3a49d74844d2a8f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_QSPIDMA_FUTURE_ECO.  <a href="#ga4332dd0868d1843ae3a49d74844d2a8f">More...</a><br /></td></tr>
<tr class="separator:ga4332dd0868d1843ae3a49d74844d2a8f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab88bcdb0f53b21b79cd0805cfd14cb89"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gab88bcdb0f53b21b79cd0805cfd14cb89">XQspiPsu_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;XQspiPsu_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:gab88bcdb0f53b21b79cd0805cfd14cb89"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read a register.  <a href="#gab88bcdb0f53b21b79cd0805cfd14cb89">More...</a><br /></td></tr>
<tr class="separator:gab88bcdb0f53b21b79cd0805cfd14cb89"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga584ee0482b95d3f49353438ca58fb180"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga584ee0482b95d3f49353438ca58fb180">XQspiPsu_WriteReg</a>(BaseAddress,  RegOffset,  RegisterValue)&#160;&#160;&#160;XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue))</td></tr>
<tr class="memdesc:ga584ee0482b95d3f49353438ca58fb180"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write to a register.  <a href="#ga584ee0482b95d3f49353438ca58fb180">More...</a><br /></td></tr>
<tr class="separator:ga584ee0482b95d3f49353438ca58fb180"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
Typedefs</h2></td></tr>
<tr class="memitem:ga6af4d9d05fc91cdef8a59c46b026c3b6"><td class="memItemLeft" align="right" valign="top">typedef void(*&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga6af4d9d05fc91cdef8a59c46b026c3b6">XQspiPsu_StatusHandler</a>) (void *CallBackRef, u32 StatusEvent, u32 ByteCount)</td></tr>
<tr class="memdesc:ga6af4d9d05fc91cdef8a59c46b026c3b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">The handler data type allows the user to define a callback function to handle the asynchronous processing for the QSPIPSU device.  <a href="#ga6af4d9d05fc91cdef8a59c46b026c3b6">More...</a><br /></td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga78067f00df477a415138cf035d5c3c1c"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga78067f00df477a415138cf035d5c3c1c">XQspiPsu_CfgInitialize</a> (<a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *InstancePtr, <a class="el" href="struct_x_qspi_psu___config.html">XQspiPsu_Config</a> *ConfigPtr, u32 EffectiveAddr)</td></tr>
<tr class="memdesc:ga78067f00df477a415138cf035d5c3c1c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initializes a specific <a class="el" href="struct_x_qspi_psu.html" title="The XQspiPsu driver instance data. ">XQspiPsu</a> instance such that the driver is ready to use.  <a href="#ga78067f00df477a415138cf035d5c3c1c">More...</a><br /></td></tr>
<tr class="separator:ga78067f00df477a415138cf035d5c3c1c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga799b60ee7157ed46b84475677aa0dc03"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga799b60ee7157ed46b84475677aa0dc03">XQspiPsu_Reset</a> (<a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga799b60ee7157ed46b84475677aa0dc03"><td class="mdescLeft">&#160;</td><td class="mdescRight">Resets the QSPIPSU device.  <a href="#ga799b60ee7157ed46b84475677aa0dc03">More...</a><br /></td></tr>
<tr class="separator:ga799b60ee7157ed46b84475677aa0dc03"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaa69ec6da90deb760954ea3dcfd55d7f"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gaaa69ec6da90deb760954ea3dcfd55d7f">XQspiPsu_Abort</a> (<a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *InstancePtr)</td></tr>
<tr class="memdesc:gaaa69ec6da90deb760954ea3dcfd55d7f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Aborts a transfer in progress by.  <a href="#gaaa69ec6da90deb760954ea3dcfd55d7f">More...</a><br /></td></tr>
<tr class="separator:gaaa69ec6da90deb760954ea3dcfd55d7f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga61de390e2bc4af0ce77448a46763ea39"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga61de390e2bc4af0ce77448a46763ea39">XQspiPsu_PolledTransfer</a> (<a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *InstancePtr, <a class="el" href="struct_x_qspi_psu___msg.html">XQspiPsu_Msg</a> *Msg, u32 NumMsg)</td></tr>
<tr class="memdesc:ga61de390e2bc4af0ce77448a46763ea39"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function performs a transfer on the bus in polled mode.  <a href="#ga61de390e2bc4af0ce77448a46763ea39">More...</a><br /></td></tr>
<tr class="separator:ga61de390e2bc4af0ce77448a46763ea39"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6ae727534cf55b878b9b1974dc72a625"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga6ae727534cf55b878b9b1974dc72a625">XQspiPsu_InterruptTransfer</a> (<a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *InstancePtr, <a class="el" href="struct_x_qspi_psu___msg.html">XQspiPsu_Msg</a> *Msg, u32 NumMsg)</td></tr>
<tr class="memdesc:ga6ae727534cf55b878b9b1974dc72a625"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function initiates a transfer on the bus and enables interrupts.  <a href="#ga6ae727534cf55b878b9b1974dc72a625">More...</a><br /></td></tr>
<tr class="separator:ga6ae727534cf55b878b9b1974dc72a625"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa345ea3ab3694a94a60e6217cb8d5e59"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gaa345ea3ab3694a94a60e6217cb8d5e59">XQspiPsu_InterruptHandler</a> (<a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *InstancePtr)</td></tr>
<tr class="memdesc:gaa345ea3ab3694a94a60e6217cb8d5e59"><td class="mdescLeft">&#160;</td><td class="mdescRight">Handles interrupt based transfers by acting on GENFIFO and DMA interurpts.  <a href="#gaa345ea3ab3694a94a60e6217cb8d5e59">More...</a><br /></td></tr>
<tr class="separator:gaa345ea3ab3694a94a60e6217cb8d5e59"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga02ea5e95c8939c2be78d26c255a6ba6f"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga02ea5e95c8939c2be78d26c255a6ba6f">XQspiPsu_SetStatusHandler</a> (<a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *InstancePtr, void *CallBackRef, <a class="el" href="group__qspipsu__v1__0.html#ga6af4d9d05fc91cdef8a59c46b026c3b6">XQspiPsu_StatusHandler</a> FuncPointer)</td></tr>
<tr class="memdesc:ga02ea5e95c8939c2be78d26c255a6ba6f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to upper layer software.  <a href="#ga02ea5e95c8939c2be78d26c255a6ba6f">More...</a><br /></td></tr>
<tr class="separator:ga02ea5e95c8939c2be78d26c255a6ba6f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafd84d3f23643ccbcbd4637f786ba48fa"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_qspi_psu___config.html">XQspiPsu_Config</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gafd84d3f23643ccbcbd4637f786ba48fa">XQspiPsu_LookupConfig</a> (u16 DeviceId)</td></tr>
<tr class="memdesc:gafd84d3f23643ccbcbd4637f786ba48fa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Looks up the device configuration based on the unique device ID.  <a href="#gafd84d3f23643ccbcbd4637f786ba48fa">More...</a><br /></td></tr>
<tr class="separator:gafd84d3f23643ccbcbd4637f786ba48fa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga689024c6f3c692877527bccc85c44e77"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga689024c6f3c692877527bccc85c44e77">XQspiPsu_SetClkPrescaler</a> (<a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *InstancePtr, u8 Prescaler)</td></tr>
<tr class="memdesc:ga689024c6f3c692877527bccc85c44e77"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configures the clock according to the prescaler passed.  <a href="#ga689024c6f3c692877527bccc85c44e77">More...</a><br /></td></tr>
<tr class="separator:ga689024c6f3c692877527bccc85c44e77"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga28338ae42ed4f7d2685ab18de2d21128"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga28338ae42ed4f7d2685ab18de2d21128">XQspiPsu_SelectFlash</a> (<a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *InstancePtr, u8 FlashCS, u8 FlashBus)</td></tr>
<tr class="memdesc:ga28338ae42ed4f7d2685ab18de2d21128"><td class="mdescLeft">&#160;</td><td class="mdescRight">This funciton should be used to tell the QSPIPSU driver the HW flash configuration being used.  <a href="#ga28338ae42ed4f7d2685ab18de2d21128">More...</a><br /></td></tr>
<tr class="separator:ga28338ae42ed4f7d2685ab18de2d21128"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad0fea713a1ec2a4ce6159439e30f7cd7"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gad0fea713a1ec2a4ce6159439e30f7cd7">XQspiPsu_SetOptions</a> (<a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *InstancePtr, u32 Options)</td></tr>
<tr class="memdesc:gad0fea713a1ec2a4ce6159439e30f7cd7"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the options for the QSPIPSU device driver.The options control how the device behaves relative to the QSPIPSU bus.  <a href="#gad0fea713a1ec2a4ce6159439e30f7cd7">More...</a><br /></td></tr>
<tr class="separator:gad0fea713a1ec2a4ce6159439e30f7cd7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0948cd1e33a60561c808e681306bcc65"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga0948cd1e33a60561c808e681306bcc65">XQspiPsu_ClearOptions</a> (<a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *InstancePtr, u32 Options)</td></tr>
<tr class="memdesc:ga0948cd1e33a60561c808e681306bcc65"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function resets the options for the QSPIPSU device driver.The options control how the device behaves relative to the QSPIPSU bus.  <a href="#ga0948cd1e33a60561c808e681306bcc65">More...</a><br /></td></tr>
<tr class="separator:ga0948cd1e33a60561c808e681306bcc65"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4a71a2847d3d2e11d9c69c29084e38df"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga4a71a2847d3d2e11d9c69c29084e38df">XQspiPsu_GetOptions</a> (<a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga4a71a2847d3d2e11d9c69c29084e38df"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function gets the options for the QSPIPSU device.  <a href="#ga4a71a2847d3d2e11d9c69c29084e38df">More...</a><br /></td></tr>
<tr class="separator:ga4a71a2847d3d2e11d9c69c29084e38df"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3a37a08570be55ea07945a18a80306f3"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga3a37a08570be55ea07945a18a80306f3">XQspiPsu_SetReadMode</a> (<a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *InstancePtr, u32 Mode)</td></tr>
<tr class="memdesc:ga3a37a08570be55ea07945a18a80306f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the Read mode for the QSPIPSU device driver.The device must be idle rather than busy transferring data before setting Read mode options.  <a href="#ga3a37a08570be55ea07945a18a80306f3">More...</a><br /></td></tr>
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</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="var-members"></a>
Variables</h2></td></tr>
<tr class="memitem:ga0a1440bbf114a2e065b65bca531a14c3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_qspi_psu___config.html">XQspiPsu_Config</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga0a1440bbf114a2e065b65bca531a14c3">XQspiPsu_ConfigTable</a> [XPAR_XQSPIPSU_NUM_INSTANCES]</td></tr>
<tr class="memdesc:ga0a1440bbf114a2e065b65bca531a14c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">This table contains configuration information for each QSPIPSU device in the system.  <a href="#ga0a1440bbf114a2e065b65bca531a14c3">More...</a><br /></td></tr>
<tr class="separator:ga0a1440bbf114a2e065b65bca531a14c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a1440bbf114a2e065b65bca531a14c3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_qspi_psu___config.html">XQspiPsu_Config</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga0a1440bbf114a2e065b65bca531a14c3">XQspiPsu_ConfigTable</a> [XPAR_XQSPIPSU_NUM_INSTANCES]</td></tr>
<tr class="memdesc:ga0a1440bbf114a2e065b65bca531a14c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">This table contains configuration information for each QSPIPSU device in the system.  <a href="#ga0a1440bbf114a2e065b65bca531a14c3">More...</a><br /></td></tr>
<tr class="separator:ga0a1440bbf114a2e065b65bca531a14c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a id="ga49734e127e6359b15c1ce7f117748c36"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga49734e127e6359b15c1ce7f117748c36">&#9670;&nbsp;</a></span>XQSPIPS_BASEADDR</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">#define XQSPIPS_BASEADDR&#160;&#160;&#160;0XFF0F0000U</td>
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</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>QSPI Base Address. </p>

</div>
</div>
<a id="gab5bb698f82719c1ffdf5055dd5ebf939"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab5bb698f82719c1ffdf5055dd5ebf939">&#9670;&nbsp;</a></span>XQSPIPS_EN_REG</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPS_EN_REG&#160;&#160;&#160;( ( <a class="el" href="group__qspipsu__v1__0.html#ga49734e127e6359b15c1ce7f117748c36">XQSPIPS_BASEADDR</a> ) + 0X00000014U )</td>
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</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPS_EN_REG. </p>

</div>
</div>
<a id="ga3c05a7421b8aea31df3d026189282cce"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga3c05a7421b8aea31df3d026189282cce">&#9670;&nbsp;</a></span>XQSPIPS_LQSPI_CFG_RST_STATE</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPS_LQSPI_CFG_RST_STATE&#160;&#160;&#160;0x800238C1</td>
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      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Default LQSPI CFG value. </p>

</div>
</div>
<a id="gad327ae631cb6e447615bc9534738af72"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad327ae631cb6e447615bc9534738af72">&#9670;&nbsp;</a></span>XQSPIPS_LQSPI_CR_INST_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPS_LQSPI_CR_INST_MASK&#160;&#160;&#160;0x000000FF</td>
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</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Read instr code. </p>

</div>
</div>
<a id="ga6f187c067994aa193d43051cb5fef0db"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga6f187c067994aa193d43051cb5fef0db">&#9670;&nbsp;</a></span>XQSPIPS_LQSPI_CR_RST_STATE</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPS_LQSPI_CR_RST_STATE&#160;&#160;&#160;0x80000003</td>
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      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Default LQSPI CR value. </p>

</div>
</div>
<a id="ga137198cf9ed99131ff88af7201399ebe"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga137198cf9ed99131ff88af7201399ebe">&#9670;&nbsp;</a></span>XQSPIPSU_BASEADDR</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_BASEADDR&#160;&#160;&#160;0xFF0F0100U</td>
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</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>GQSPI Base Address. </p>

</div>
</div>
<a id="ga1d76a2f706f3988da79345132e484303"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga1d76a2f706f3988da79345132e484303">&#9670;&nbsp;</a></span>XQSPIPSU_CFG_OFFSET</h2>

<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XQSPIPSU_CFG_OFFSET&#160;&#160;&#160;0X00000000U</td>
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</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_CFG. </p>

<p class="reference">Referenced by <a class="el" href="group__qspipsu__v1__0.html#ga0948cd1e33a60561c808e681306bcc65">XQspiPsu_ClearOptions()</a>, <a class="el" href="group__qspipsu__v1__0.html#ga4a71a2847d3d2e11d9c69c29084e38df">XQspiPsu_GetOptions()</a>, <a class="el" href="group__qspipsu__v1__0.html#ga799b60ee7157ed46b84475677aa0dc03">XQspiPsu_Reset()</a>, <a class="el" href="group__qspipsu__v1__0.html#gad0fea713a1ec2a4ce6159439e30f7cd7">XQspiPsu_SetOptions()</a>, and <a class="el" href="group__qspipsu__v1__0.html#ga3a37a08570be55ea07945a18a80306f3">XQspiPsu_SetReadMode()</a>.</p>

</div>
</div>
<a id="ga5b7b95790bfeb5bfb3dfd63e4a5e76cc"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga5b7b95790bfeb5bfb3dfd63e4a5e76cc">&#9670;&nbsp;</a></span>XQSPIPSU_EN_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_EN_OFFSET&#160;&#160;&#160;0X00000014U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_EN_REG. </p>

</div>
</div>
<a id="gac14f429fa7d15b5c4bf2808ed08e7120"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac14f429fa7d15b5c4bf2808ed08e7120">&#9670;&nbsp;</a></span>XQSPIPSU_FIFO_CTRL_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_FIFO_CTRL_OFFSET&#160;&#160;&#160;0X0000004CU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_FIFO_CTRL. </p>

</div>
</div>
<a id="ga3bfe2023b6a6ce56e9d13f130bd1c86d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga3bfe2023b6a6ce56e9d13f130bd1c86d">&#9670;&nbsp;</a></span>XQSPIPSU_GEN_FIFO_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_GEN_FIFO_OFFSET&#160;&#160;&#160;0X00000040U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_GEN_FIFO. </p>

</div>
</div>
<a id="gadda8c30c269feb26bc40f588da2c6097"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gadda8c30c269feb26bc40f588da2c6097">&#9670;&nbsp;</a></span>XQSPIPSU_GF_SNAPSHOT_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_GF_SNAPSHOT_OFFSET&#160;&#160;&#160;0X00000060U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_GF_SNAPSHOT. </p>

</div>
</div>
<a id="ga5a8034417fd3c9846c968679c1cad859"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga5a8034417fd3c9846c968679c1cad859">&#9670;&nbsp;</a></span>XQSPIPSU_GF_THRESHOLD_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_GF_THRESHOLD_OFFSET&#160;&#160;&#160;0X00000050U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_GF_THRESHOLD. </p>

</div>
</div>
<a id="gad50a54ee932051b2fed093ef6f2e8a12"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad50a54ee932051b2fed093ef6f2e8a12">&#9670;&nbsp;</a></span>XQSPIPSU_GPIO_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_GPIO_OFFSET&#160;&#160;&#160;0X00000030U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_GPIO. </p>

</div>
</div>
<a id="ga5eb684785dfb0a249b18126089624b91"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga5eb684785dfb0a249b18126089624b91">&#9670;&nbsp;</a></span>XQSPIPSU_IDR_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_IDR_OFFSET&#160;&#160;&#160;0X0000000CU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_IDR. </p>

</div>
</div>
<a id="gab8e3a4621239cb556fc8acdd0a6d10b6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab8e3a4621239cb556fc8acdd0a6d10b6">&#9670;&nbsp;</a></span>XQSPIPSU_IER_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_IER_OFFSET&#160;&#160;&#160;0X00000008U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_IER. </p>

</div>
</div>
<a id="ga1711ff533a11dd37b3d72056050025e5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga1711ff533a11dd37b3d72056050025e5">&#9670;&nbsp;</a></span>XQSPIPSU_IMR_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_IMR_OFFSET&#160;&#160;&#160;0X00000010U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_IMR. </p>

</div>
</div>
<a id="gadae24d033fb12577e3e4eda5427a950a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gadae24d033fb12577e3e4eda5427a950a">&#9670;&nbsp;</a></span>XQSPIPSU_ISR_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_ISR_OFFSET&#160;&#160;&#160;0X00000004U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_ISR. </p>

<p class="reference">Referenced by <a class="el" href="group__qspipsu__v1__0.html#gaaa69ec6da90deb760954ea3dcfd55d7f">XQspiPsu_Abort()</a>, and <a class="el" href="group__qspipsu__v1__0.html#gaa345ea3ab3694a94a60e6217cb8d5e59">XQspiPsu_InterruptHandler()</a>.</p>

</div>
</div>
<a id="ga4636d144794bb35424cacd6f6d49781a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga4636d144794bb35424cacd6f6d49781a">&#9670;&nbsp;</a></span>XQSPIPSU_LPBK_DLY_ADJ_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_LPBK_DLY_ADJ_OFFSET&#160;&#160;&#160;0X00000038U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_LPBK_DLY_ADJ. </p>

</div>
</div>
<a id="ga5406192835c4f1d618b56626790628b1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga5406192835c4f1d618b56626790628b1">&#9670;&nbsp;</a></span>XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK&#160;&#160;&#160;0x01000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Upper memory page. </p>

</div>
</div>
<a id="gac5bfff58ddca187becec7c533cf355fe"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac5bfff58ddca187becec7c533cf355fe">&#9670;&nbsp;</a></span>XQSPIPSU_LQSPI_CR_LINEAR_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_LQSPI_CR_LINEAR_MASK&#160;&#160;&#160;0x80000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>LQSPI mode enable. </p>

</div>
</div>
<a id="gad3cd6ea3b67401b777b26365937e9c97"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad3cd6ea3b67401b777b26365937e9c97">&#9670;&nbsp;</a></span>XQSPIPSU_LQSPI_CR_MODE_BITS_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_LQSPI_CR_MODE_BITS_MASK&#160;&#160;&#160;0x00FF0000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Mode value for dual I/O or quad I/O. </p>

</div>
</div>
<a id="ga0eecbc04289c520b605393012c8715ff"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga0eecbc04289c520b605393012c8715ff">&#9670;&nbsp;</a></span>XQSPIPSU_LQSPI_CR_MODE_EN_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_LQSPI_CR_MODE_EN_MASK&#160;&#160;&#160;0x02000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Enable mode bits. </p>

</div>
</div>
<a id="ga40238108ef1f0763edaf8adc59c03d72"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga40238108ef1f0763edaf8adc59c03d72">&#9670;&nbsp;</a></span>XQSPIPSU_LQSPI_CR_MODE_ON_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_LQSPI_CR_MODE_ON_MASK&#160;&#160;&#160;0x01000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Mode on. </p>

</div>
</div>
<a id="ga02a2df38913ec3616e70351637cbbb50"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga02a2df38913ec3616e70351637cbbb50">&#9670;&nbsp;</a></span>XQSPIPSU_LQSPI_CR_OFFSET <span class="overload">[1/2]</span></h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_LQSPI_CR_OFFSET&#160;&#160;&#160;0X000000A0U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_CFG. </p>

</div>
</div>
<a id="ga02a2df38913ec3616e70351637cbbb50"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga02a2df38913ec3616e70351637cbbb50">&#9670;&nbsp;</a></span>XQSPIPSU_LQSPI_CR_OFFSET <span class="overload">[2/2]</span></h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_LQSPI_CR_OFFSET&#160;&#160;&#160;0X000000A0U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_CFG. </p>

</div>
</div>
<a id="ga66a4736f3e48910c8ba8dc2999b16558"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga66a4736f3e48910c8ba8dc2999b16558">&#9670;&nbsp;</a></span>XQSPIPSU_LQSPI_CR_SEP_BUS_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_LQSPI_CR_SEP_BUS_MASK&#160;&#160;&#160;0x20000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Seperate memory bus. </p>

</div>
</div>
<a id="ga6fbc52b88d443b2a5ea258ff83ef71f2"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga6fbc52b88d443b2a5ea258ff83ef71f2">&#9670;&nbsp;</a></span>XQSPIPSU_LQSPI_CR_TWO_MEM_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_LQSPI_CR_TWO_MEM_MASK&#160;&#160;&#160;0x40000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Both memories or one. </p>

</div>
</div>
<a id="gaa7502d70b7ddd899d5bf8bba3f23d70e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaa7502d70b7ddd899d5bf8bba3f23d70e">&#9670;&nbsp;</a></span>XQSPIPSU_LQSPI_CR_U_PAGE_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_LQSPI_CR_U_PAGE_MASK&#160;&#160;&#160;0x10000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Upper memory page. </p>

</div>
</div>
<a id="ga9dae139fcca838438b3e14f4306f1f06"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga9dae139fcca838438b3e14f4306f1f06">&#9670;&nbsp;</a></span>XQSPIPSU_MOD_ID_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_MOD_ID_OFFSET&#160;&#160;&#160;0X000000FCU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_MOD_ID. </p>

</div>
</div>
<a id="ga311de6f25e5cf64057e9ba429cf86507"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga311de6f25e5cf64057e9ba429cf86507">&#9670;&nbsp;</a></span>XQSPIPSU_P_TO_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_P_TO_OFFSET&#160;&#160;&#160;0X00000058U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_P_TIMEOUT. </p>

</div>
</div>
<a id="gaf657fc3a38e22e512c0f7cf03bda1ad7"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaf657fc3a38e22e512c0f7cf03bda1ad7">&#9670;&nbsp;</a></span>XQSPIPSU_POLL_CFG_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_POLL_CFG_OFFSET&#160;&#160;&#160;0X00000054U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_POLL_CFG. </p>

</div>
</div>
<a id="ga39b0151b1cd09cb2da8d67efeb8ec0cb"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga39b0151b1cd09cb2da8d67efeb8ec0cb">&#9670;&nbsp;</a></span>XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET&#160;&#160;&#160;0X00000728U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_QSPIDMA_DST_ADDR_MSB. </p>

</div>
</div>
<a id="ga3b9c82ef758ea9e8bfda707130051091"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga3b9c82ef758ea9e8bfda707130051091">&#9670;&nbsp;</a></span>XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET&#160;&#160;&#160;0X00000700U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_QSPIDMA_DST_ADDR. </p>

</div>
</div>
<a id="gad11e1e53c55440afa41685846b74c9c7"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad11e1e53c55440afa41685846b74c9c7">&#9670;&nbsp;</a></span>XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET&#160;&#160;&#160;0X00000724U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_QSPIDMA_DST_CTRL2. </p>

</div>
</div>
<a id="ga1c49b7d688c394b3bb37d4293fa34df5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga1c49b7d688c394b3bb37d4293fa34df5">&#9670;&nbsp;</a></span>XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET&#160;&#160;&#160;0X0000070CU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_QSPIDMA_DST_CTRL. </p>

</div>
</div>
<a id="ga04b009825df34055ec8a92ac44e651fa"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga04b009825df34055ec8a92ac44e651fa">&#9670;&nbsp;</a></span>XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET&#160;&#160;&#160;0X0000071CU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_QSPIDMA_DST_I_DIS. </p>

</div>
</div>
<a id="gaceea2425458ac2a40305f93e496865a9"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaceea2425458ac2a40305f93e496865a9">&#9670;&nbsp;</a></span>XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET&#160;&#160;&#160;0X00000718U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_QSPIDMA_DST_I_EN. </p>

</div>
</div>
<a id="ga7fcb2a02499c783baa52e6dbba23e228"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga7fcb2a02499c783baa52e6dbba23e228">&#9670;&nbsp;</a></span>XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET&#160;&#160;&#160;0X00000714U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_QSPIDMA_DST_I_STS. </p>

</div>
</div>
<a id="ga30ca967a9288020ef44470e6f09c2b6b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga30ca967a9288020ef44470e6f09c2b6b">&#9670;&nbsp;</a></span>XQSPIPSU_QSPIDMA_DST_IMR_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_QSPIDMA_DST_IMR_OFFSET&#160;&#160;&#160;0X00000720U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_QSPIDMA_DST_IMR. </p>

</div>
</div>
<a id="gab2dea188a0404d6e555c4ff2839eb86a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab2dea188a0404d6e555c4ff2839eb86a">&#9670;&nbsp;</a></span>XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET&#160;&#160;&#160;0X00000704U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_QSPIDMA_DST_SIZE. </p>

</div>
</div>
<a id="ga8fd8100c320c3da46a93af5adf6592f0"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga8fd8100c320c3da46a93af5adf6592f0">&#9670;&nbsp;</a></span>XQSPIPSU_QSPIDMA_DST_STS_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_QSPIDMA_DST_STS_OFFSET&#160;&#160;&#160;0X00000708U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_QSPIDMA_DST_STS. </p>

</div>
</div>
<a id="ga4332dd0868d1843ae3a49d74844d2a8f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga4332dd0868d1843ae3a49d74844d2a8f">&#9670;&nbsp;</a></span>XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET&#160;&#160;&#160;0X00000EFCU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_QSPIDMA_FUTURE_ECO. </p>

</div>
</div>
<a id="gab88bcdb0f53b21b79cd0805cfd14cb89"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab88bcdb0f53b21b79cd0805cfd14cb89">&#9670;&nbsp;</a></span>XQspiPsu_ReadReg</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQspiPsu_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;XQspiPsu_In32((BaseAddress) + (RegOffset))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Read a register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>contains the base address of the device. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>contains the offset from the 1st register of the device to the target register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The value read from the register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-Style signature: u32 XQspiPsu_ReadReg(u32 BaseAddress. s32 RegOffset) </dd></dl>

<p class="reference">Referenced by <a class="el" href="group__qspipsu__v1__0.html#gaaa69ec6da90deb760954ea3dcfd55d7f">XQspiPsu_Abort()</a>, <a class="el" href="group__qspipsu__v1__0.html#ga0948cd1e33a60561c808e681306bcc65">XQspiPsu_ClearOptions()</a>, <a class="el" href="group__qspipsu__v1__0.html#ga4a71a2847d3d2e11d9c69c29084e38df">XQspiPsu_GetOptions()</a>, <a class="el" href="group__qspipsu__v1__0.html#gaa345ea3ab3694a94a60e6217cb8d5e59">XQspiPsu_InterruptHandler()</a>, <a class="el" href="group__qspipsu__v1__0.html#ga799b60ee7157ed46b84475677aa0dc03">XQspiPsu_Reset()</a>, <a class="el" href="group__qspipsu__v1__0.html#gad0fea713a1ec2a4ce6159439e30f7cd7">XQspiPsu_SetOptions()</a>, and <a class="el" href="group__qspipsu__v1__0.html#ga3a37a08570be55ea07945a18a80306f3">XQspiPsu_SetReadMode()</a>.</p>

</div>
</div>
<a id="ga419ba63e8028ea7e8aa833523ea3a785"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga419ba63e8028ea7e8aa833523ea3a785">&#9670;&nbsp;</a></span>XQSPIPSU_RX_COPY_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_RX_COPY_OFFSET&#160;&#160;&#160;0X00000064U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_RX_COPY. </p>

</div>
</div>
<a id="ga97be55c27b71a154877fb5f919d627f1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga97be55c27b71a154877fb5f919d627f1">&#9670;&nbsp;</a></span>XQSPIPSU_RX_THRESHOLD_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_RX_THRESHOLD_OFFSET&#160;&#160;&#160;0X0000002CU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_RX_THRESHOLD. </p>

</div>
</div>
<a id="ga68b0b4316693414546980dea7baaf0a4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga68b0b4316693414546980dea7baaf0a4">&#9670;&nbsp;</a></span>XQSPIPSU_RXD_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_RXD_OFFSET&#160;&#160;&#160;0X00000020U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_RXD. </p>

</div>
</div>
<a id="ga84156abbc51d17b988b1e82c584be10d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga84156abbc51d17b988b1e82c584be10d">&#9670;&nbsp;</a></span>XQSPIPSU_SEL_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_SEL_OFFSET&#160;&#160;&#160;0X00000044U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_SEL. </p>

</div>
</div>
<a id="ga33bc760357127168b3a665f969036421"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga33bc760357127168b3a665f969036421">&#9670;&nbsp;</a></span>XQSPIPSU_TX_THRESHOLD_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_TX_THRESHOLD_OFFSET&#160;&#160;&#160;0X00000028U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_TX_THRESHOLD. </p>

</div>
</div>
<a id="ga4884f0160746c6696598ef6dda1fc9ff"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga4884f0160746c6696598ef6dda1fc9ff">&#9670;&nbsp;</a></span>XQSPIPSU_TXD_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_TXD_OFFSET&#160;&#160;&#160;0X0000001CU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_TXD. </p>

</div>
</div>
<a id="ga584ee0482b95d3f49353438ca58fb180"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga584ee0482b95d3f49353438ca58fb180">&#9670;&nbsp;</a></span>XQspiPsu_WriteReg</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQspiPsu_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegisterValue&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Write to a register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>contains the base address of the device. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>contains the offset from the 1st register of the device to target register. </td></tr>
    <tr><td class="paramname">RegisterValue</td><td>is the value to be written to the register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-Style signature: void XQspiPsu_WriteReg(u32 BaseAddress, s32 RegOffset, u32 RegisterValue) </dd></dl>

<p class="reference">Referenced by <a class="el" href="group__qspipsu__v1__0.html#gaaa69ec6da90deb760954ea3dcfd55d7f">XQspiPsu_Abort()</a>.</p>

</div>
</div>
<a id="ga4951a0b7d9ce35780f74864a196092e4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga4951a0b7d9ce35780f74864a196092e4">&#9670;&nbsp;</a></span>XQSPIPSU_XFER_STS_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XQSPIPSU_XFER_STS_OFFSET&#160;&#160;&#160;0X0000005CU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu__hw_8h.html">xqspipsu_hw.h</a>&gt;</code></p>

<p>Register: XQSPIPSU_XFER_STS. </p>

</div>
</div>
<h2 class="groupheader">Typedef Documentation</h2>
<a id="ga6af4d9d05fc91cdef8a59c46b026c3b6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga6af4d9d05fc91cdef8a59c46b026c3b6">&#9670;&nbsp;</a></span>XQspiPsu_StatusHandler</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">typedef void(* XQspiPsu_StatusHandler) (void *CallBackRef, u32 StatusEvent, u32 ByteCount)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu_8h.html">xqspipsu.h</a>&gt;</code></p>

<p>The handler data type allows the user to define a callback function to handle the asynchronous processing for the QSPIPSU device. </p>
<p>The application using this driver is expected to define a handler of this type to support interrupt driven mode. The handler executes in an interrupt context, so only minimal processing should be performed.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">CallBackRef</td><td>is the callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked. Its type is not important to the driver, so it is a void pointer. </td></tr>
    <tr><td class="paramname">StatusEvent</td><td>holds one or more status events that have occurred. See the <a class="el" href="group__qspipsu__v1__0.html#ga02ea5e95c8939c2be78d26c255a6ba6f" title="Sets the status callback function, the status handler, which the driver calls when it encounters cond...">XQspiPsu_SetStatusHandler()</a> for details on the status events that can be passed in the callback. </td></tr>
    <tr><td class="paramname">ByteCount</td><td>indicates how many bytes of data were successfully transferred. This may be less than the number of bytes requested if the status event indicates an error. </td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
<h2 class="groupheader">Function Documentation</h2>
<a id="gaaa69ec6da90deb760954ea3dcfd55d7f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaaa69ec6da90deb760954ea3dcfd55d7f">&#9670;&nbsp;</a></span>XQspiPsu_Abort()</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void XQspiPsu_Abort </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu_8c.html">xqspipsu.c</a>&gt;</code></p>

<p>Aborts a transfer in progress by. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_qspi_psu.html" title="The XQspiPsu driver instance data. ">XQspiPsu</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd></dd></dl>

<p class="reference">References <a class="el" href="struct_x_qspi_psu___config.html#a4fe2b57911aede873cac306ec0b295ad">XQspiPsu_Config::BaseAddress</a>, <a class="el" href="struct_x_qspi_psu.html#a9b3aa272eb335fecaaa8f47fd2ed9241">XQspiPsu::Config</a>, <a class="el" href="group__qspipsu__v1__0.html#gadae24d033fb12577e3e4eda5427a950a">XQSPIPSU_ISR_OFFSET</a>, <a class="el" href="group__qspipsu__v1__0.html#gab88bcdb0f53b21b79cd0805cfd14cb89">XQspiPsu_ReadReg</a>, and <a class="el" href="group__qspipsu__v1__0.html#ga584ee0482b95d3f49353438ca58fb180">XQspiPsu_WriteReg</a>.</p>

<p class="reference">Referenced by <a class="el" href="group__qspipsu__v1__0.html#ga799b60ee7157ed46b84475677aa0dc03">XQspiPsu_Reset()</a>.</p>

</div>
</div>
<a id="ga78067f00df477a415138cf035d5c3c1c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga78067f00df477a415138cf035d5c3c1c">&#9670;&nbsp;</a></span>XQspiPsu_CfgInitialize()</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">s32 XQspiPsu_CfgInitialize </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_qspi_psu___config.html">XQspiPsu_Config</a> *&#160;</td>
          <td class="paramname"><em>ConfigPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>EffectiveAddr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu_8c.html">xqspipsu.c</a>&gt;</code></p>

<p>Initializes a specific <a class="el" href="struct_x_qspi_psu.html" title="The XQspiPsu driver instance data. ">XQspiPsu</a> instance such that the driver is ready to use. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_qspi_psu.html" title="The XQspiPsu driver instance data. ">XQspiPsu</a> instance. </td></tr>
    <tr><td class="paramname">ConfigPtr</td><td>is a reference to a structure containing information about a specific QSPIPSU device. This function initializes an InstancePtr object for a specific device specified by the contents of Config. </td></tr>
    <tr><td class="paramname">EffectiveAddr</td><td>is the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, use ConfigPtr-&gt;Config.BaseAddress for this device.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if successful.</li>
<li>XST_DEVICE_IS_STARTED if the device is already started. It must be stopped to re-initialize.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_qspi_psu___config.html#a4fe2b57911aede873cac306ec0b295ad">XQspiPsu_Config::BaseAddress</a>, <a class="el" href="struct_x_qspi_psu.html#a9b3aa272eb335fecaaa8f47fd2ed9241">XQspiPsu::Config</a>, and <a class="el" href="struct_x_qspi_psu.html#ab6f2b5a35423f4a2c34053eaeec3dcd6">XQspiPsu::IsBusy</a>.</p>

</div>
</div>
<a id="ga0948cd1e33a60561c808e681306bcc65"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga0948cd1e33a60561c808e681306bcc65">&#9670;&nbsp;</a></span>XQspiPsu_ClearOptions()</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">s32 XQspiPsu_ClearOptions </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Options</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p><code>#include &lt;<a class="el" href="xqspipsu_8h.html">xqspipsu.h</a>&gt;</code></p>

<p>This function resets the options for the QSPIPSU device driver.The options control how the device behaves relative to the QSPIPSU bus. </p>
<p>The device must be idle rather than busy transferring data before setting these device options.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_qspi_psu.html" title="The XQspiPsu driver instance data. ">XQspiPsu</a> instance. </td></tr>
    <tr><td class="paramname">Options</td><td>contains the specified options to be set. This is a bit mask where a 1 indicates the option should be turned OFF and a 0 indicates no action. One or more bit values may be contained in the mask. See the bit definitions named XQSPIPSU_*_OPTIONS in the file <a class="el" href="xqspipsu_8h.html">xqspipsu.h</a>.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if options are successfully set.</li>
<li>XST_DEVICE_BUSY if the device is currently transferring data. The transfer must complete or be aborted before setting options.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function is not thread-safe. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_qspi_psu___config.html#a4fe2b57911aede873cac306ec0b295ad">XQspiPsu_Config::BaseAddress</a>, <a class="el" href="struct_x_qspi_psu.html#a9b3aa272eb335fecaaa8f47fd2ed9241">XQspiPsu::Config</a>, <a class="el" href="struct_x_qspi_psu.html#ab6f2b5a35423f4a2c34053eaeec3dcd6">XQspiPsu::IsBusy</a>, <a class="el" href="struct_x_qspi_psu.html#ae6039f5b4f8cdf2e528931ec383deb31">XQspiPsu::IsReady</a>, <a class="el" href="group__qspipsu__v1__0.html#ga1d76a2f706f3988da79345132e484303">XQSPIPSU_CFG_OFFSET</a>, and <a class="el" href="group__qspipsu__v1__0.html#gab88bcdb0f53b21b79cd0805cfd14cb89">XQspiPsu_ReadReg</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga4a71a2847d3d2e11d9c69c29084e38df">&#9670;&nbsp;</a></span>XQspiPsu_GetOptions()</h2>

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          <td class="memname">u32 XQspiPsu_GetOptions </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xqspipsu_8h.html">xqspipsu.h</a>&gt;</code></p>

<p>This function gets the options for the QSPIPSU device. </p>
<p>The options control how the device behaves relative to the QSPIPSU bus.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_qspi_psu.html" title="The XQspiPsu driver instance data. ">XQspiPsu</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<p>Options contains the specified options currently set. This is a bit value where a 1 means the option is on, and a 0 means the option is off. See the bit definitions named XQSPIPSU_*_OPTIONS in file <a class="el" href="xqspipsu_8h.html">xqspipsu.h</a>.</p>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_qspi_psu___config.html#a4fe2b57911aede873cac306ec0b295ad">XQspiPsu_Config::BaseAddress</a>, <a class="el" href="struct_x_qspi_psu.html#a9b3aa272eb335fecaaa8f47fd2ed9241">XQspiPsu::Config</a>, <a class="el" href="struct_x_qspi_psu.html#ae6039f5b4f8cdf2e528931ec383deb31">XQspiPsu::IsReady</a>, <a class="el" href="group__qspipsu__v1__0.html#ga1d76a2f706f3988da79345132e484303">XQSPIPSU_CFG_OFFSET</a>, and <a class="el" href="group__qspipsu__v1__0.html#gab88bcdb0f53b21b79cd0805cfd14cb89">XQspiPsu_ReadReg</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gaa345ea3ab3694a94a60e6217cb8d5e59">&#9670;&nbsp;</a></span>XQspiPsu_InterruptHandler()</h2>

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          <td class="memname">s32 XQspiPsu_InterruptHandler </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xqspipsu_8c.html">xqspipsu.c</a>&gt;</code></p>

<p>Handles interrupt based transfers by acting on GENFIFO and DMA interurpts. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_qspi_psu.html" title="The XQspiPsu driver instance data. ">XQspiPsu</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if successful.</li>
<li>XST_FAILURE if transfer fails.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_qspi_psu___config.html#a4fe2b57911aede873cac306ec0b295ad">XQspiPsu_Config::BaseAddress</a>, <a class="el" href="struct_x_qspi_psu.html#a9b3aa272eb335fecaaa8f47fd2ed9241">XQspiPsu::Config</a>, <a class="el" href="struct_x_qspi_psu.html#abcf49b02b0b90a7eecf9fb5ba40ac0b3">XQspiPsu::ReadMode</a>, <a class="el" href="group__qspipsu__v1__0.html#gadae24d033fb12577e3e4eda5427a950a">XQSPIPSU_ISR_OFFSET</a>, and <a class="el" href="group__qspipsu__v1__0.html#gab88bcdb0f53b21b79cd0805cfd14cb89">XQspiPsu_ReadReg</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga6ae727534cf55b878b9b1974dc72a625">&#9670;&nbsp;</a></span>XQspiPsu_InterruptTransfer()</h2>

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          <td class="memname">s32 XQspiPsu_InterruptTransfer </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_qspi_psu___msg.html">XQspiPsu_Msg</a> *&#160;</td>
          <td class="paramname"><em>Msg</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>NumMsg</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu_8c.html">xqspipsu.c</a>&gt;</code></p>

<p>This function initiates a transfer on the bus and enables interrupts. </p>
<p>The transfer is completed by the interrupt handler. The messages passed are all transferred on the bus between one CS assert and de-assert.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_qspi_psu.html" title="The XQspiPsu driver instance data. ">XQspiPsu</a> instance. </td></tr>
    <tr><td class="paramname">Msg</td><td>is a pointer to the structure containing transfer data. </td></tr>
    <tr><td class="paramname">NumMsg</td><td>is the number of messages to be transferred.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if successful.</li>
<li>XST_FAILURE if transfer fails.</li>
<li>XST_DEVICE_BUSY if a transfer is already in progress.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_qspi_psu.html#ab6f2b5a35423f4a2c34053eaeec3dcd6">XQspiPsu::IsBusy</a>, and <a class="el" href="struct_x_qspi_psu.html#ae6039f5b4f8cdf2e528931ec383deb31">XQspiPsu::IsReady</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gafd84d3f23643ccbcbd4637f786ba48fa">&#9670;&nbsp;</a></span>XQspiPsu_LookupConfig()</h2>

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          <td class="memname"><a class="el" href="struct_x_qspi_psu___config.html">XQspiPsu_Config</a> * XQspiPsu_LookupConfig </td>
          <td>(</td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>DeviceId</em></td><td>)</td>
          <td></td>
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<p><code>#include &lt;<a class="el" href="xqspipsu_8h.html">xqspipsu.h</a>&gt;</code></p>

<p>Looks up the device configuration based on the unique device ID. </p>
<p>A table contains the configuration info for each device in the system.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DeviceId</td><td>contains the ID of the device to look up the configuration for.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<p>A pointer to the configuration found or NULL if the specified device ID was not found. See <a class="el" href="xqspipsu_8h.html">xqspipsu.h</a> for the definition of <a class="el" href="struct_x_qspi_psu___config.html" title="This typedef contains configuration information for the device. ">XQspiPsu_Config</a>.</p>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga61de390e2bc4af0ce77448a46763ea39">&#9670;&nbsp;</a></span>XQspiPsu_PolledTransfer()</h2>

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          <td class="memname">s32 XQspiPsu_PolledTransfer </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_qspi_psu___msg.html">XQspiPsu_Msg</a> *&#160;</td>
          <td class="paramname"><em>Msg</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>NumMsg</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu_8c.html">xqspipsu.c</a>&gt;</code></p>

<p>This function performs a transfer on the bus in polled mode. </p>
<p>The messages passed are all transferred on the bus between one CS assert and de-assert.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_qspi_psu.html" title="The XQspiPsu driver instance data. ">XQspiPsu</a> instance. </td></tr>
    <tr><td class="paramname">Msg</td><td>is a pointer to the structure containing transfer data. </td></tr>
    <tr><td class="paramname">NumMsg</td><td>is the number of messages to be transferred.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if successful.</li>
<li>XST_FAILURE if transfer fails.</li>
<li>XST_DEVICE_BUSY if a transfer is already in progress.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_qspi_psu.html#ab6f2b5a35423f4a2c34053eaeec3dcd6">XQspiPsu::IsBusy</a>, and <a class="el" href="struct_x_qspi_psu.html#ae6039f5b4f8cdf2e528931ec383deb31">XQspiPsu::IsReady</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga799b60ee7157ed46b84475677aa0dc03">&#9670;&nbsp;</a></span>XQspiPsu_Reset()</h2>

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          <td class="memname">void XQspiPsu_Reset </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xqspipsu_8c.html">xqspipsu.c</a>&gt;</code></p>

<p>Resets the QSPIPSU device. </p>
<p>Reset must only be called after the driver has been initialized. Any data transfer that is in progress is aborted.</p>
<p>The upper layer software is responsible for re-configuring (if necessary) and restarting the QSPIPSU device after the reset.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_qspi_psu.html" title="The XQspiPsu driver instance data. ">XQspiPsu</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_qspi_psu___config.html#a4fe2b57911aede873cac306ec0b295ad">XQspiPsu_Config::BaseAddress</a>, <a class="el" href="struct_x_qspi_psu.html#a9b3aa272eb335fecaaa8f47fd2ed9241">XQspiPsu::Config</a>, <a class="el" href="group__qspipsu__v1__0.html#gaaa69ec6da90deb760954ea3dcfd55d7f">XQspiPsu_Abort()</a>, <a class="el" href="group__qspipsu__v1__0.html#ga1d76a2f706f3988da79345132e484303">XQSPIPSU_CFG_OFFSET</a>, and <a class="el" href="group__qspipsu__v1__0.html#gab88bcdb0f53b21b79cd0805cfd14cb89">XQspiPsu_ReadReg</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga28338ae42ed4f7d2685ab18de2d21128">&#9670;&nbsp;</a></span>XQspiPsu_SelectFlash()</h2>

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          <td class="memname">void XQspiPsu_SelectFlash </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>FlashCS</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>FlashBus</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xqspipsu_8h.html">xqspipsu.h</a>&gt;</code></p>

<p>This funciton should be used to tell the QSPIPSU driver the HW flash configuration being used. </p>
<p>This API should be called atleast once in the application. If desired, it can be called multiple times when switching between communicating to different flahs devices/using different configs.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_qspi_psu.html" title="The XQspiPsu driver instance data. ">XQspiPsu</a> instance. </td></tr>
    <tr><td class="paramname">FlashCS</td><td>- Flash Chip Select. </td></tr>
    <tr><td class="paramname">FlashBus</td><td>- Flash Bus (Upper, Lower or Both).</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if successful.</li>
<li>XST_DEVICE_IS_STARTED if the device is already started. It must be stopped to re-initialize.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>If this funciton is not called atleast once in the application, the driver assumes there is a single flash connected to the lower bus and CS line. </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga689024c6f3c692877527bccc85c44e77">&#9670;&nbsp;</a></span>XQspiPsu_SetClkPrescaler()</h2>

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          <td class="memname">s32 XQspiPsu_SetClkPrescaler </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Prescaler</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xqspipsu_8h.html">xqspipsu.h</a>&gt;</code></p>

<p>Configures the clock according to the prescaler passed. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_qspi_psu.html" title="The XQspiPsu driver instance data. ">XQspiPsu</a> instance. </td></tr>
    <tr><td class="paramname">Prescaler</td><td>- clock prescaler to be set.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if successful.</li>
<li>XST_DEVICE_IS_STARTED if the device is already started.</li>
<li>XST_DEVICE_BUSY if the device is currently transferring data. It must be stopped to re-initialize.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_qspi_psu.html#ae6039f5b4f8cdf2e528931ec383deb31">XQspiPsu::IsReady</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gad0fea713a1ec2a4ce6159439e30f7cd7">&#9670;&nbsp;</a></span>XQspiPsu_SetOptions()</h2>

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          <td class="memname">s32 XQspiPsu_SetOptions </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Options</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xqspipsu_8h.html">xqspipsu.h</a>&gt;</code></p>

<p>This function sets the options for the QSPIPSU device driver.The options control how the device behaves relative to the QSPIPSU bus. </p>
<p>The device must be idle rather than busy transferring data before setting these device options.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_qspi_psu.html" title="The XQspiPsu driver instance data. ">XQspiPsu</a> instance. </td></tr>
    <tr><td class="paramname">Options</td><td>contains the specified options to be set. This is a bit mask where a 1 indicates the option should be turned ON and a 0 indicates no action. One or more bit values may be contained in the mask. See the bit definitions named XQSPIPSU_*_OPTIONS in the file <a class="el" href="xqspipsu_8h.html">xqspipsu.h</a>.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if options are successfully set.</li>
<li>XST_DEVICE_BUSY if the device is currently transferring data. The transfer must complete or be aborted before setting options.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function is not thread-safe. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_qspi_psu___config.html#a4fe2b57911aede873cac306ec0b295ad">XQspiPsu_Config::BaseAddress</a>, <a class="el" href="struct_x_qspi_psu.html#a9b3aa272eb335fecaaa8f47fd2ed9241">XQspiPsu::Config</a>, <a class="el" href="struct_x_qspi_psu.html#ab6f2b5a35423f4a2c34053eaeec3dcd6">XQspiPsu::IsBusy</a>, <a class="el" href="struct_x_qspi_psu.html#ae6039f5b4f8cdf2e528931ec383deb31">XQspiPsu::IsReady</a>, <a class="el" href="group__qspipsu__v1__0.html#ga1d76a2f706f3988da79345132e484303">XQSPIPSU_CFG_OFFSET</a>, and <a class="el" href="group__qspipsu__v1__0.html#gab88bcdb0f53b21b79cd0805cfd14cb89">XQspiPsu_ReadReg</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga3a37a08570be55ea07945a18a80306f3">&#9670;&nbsp;</a></span>XQspiPsu_SetReadMode()</h2>

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          <td class="memname">s32 XQspiPsu_SetReadMode </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
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          <td class="paramkey"></td>
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          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Mode</em>&#160;</td>
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<p><code>#include &lt;<a class="el" href="xqspipsu_8h.html">xqspipsu.h</a>&gt;</code></p>

<p>This function sets the Read mode for the QSPIPSU device driver.The device must be idle rather than busy transferring data before setting Read mode options. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_qspi_psu.html" title="The XQspiPsu driver instance data. ">XQspiPsu</a> instance. </td></tr>
    <tr><td class="paramname">Mode</td><td>contains the specified Mode to be set. See the bit definitions named XQSPIPSU_READMODE_* in the file <a class="el" href="xqspipsu_8h.html">xqspipsu.h</a>.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if options are successfully set.</li>
<li>XST_DEVICE_BUSY if the device is currently transferring data. The transfer must complete or be aborted before setting Mode.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function is not thread-safe. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_qspi_psu___config.html#a4fe2b57911aede873cac306ec0b295ad">XQspiPsu_Config::BaseAddress</a>, <a class="el" href="struct_x_qspi_psu.html#a9b3aa272eb335fecaaa8f47fd2ed9241">XQspiPsu::Config</a>, <a class="el" href="struct_x_qspi_psu.html#ab6f2b5a35423f4a2c34053eaeec3dcd6">XQspiPsu::IsBusy</a>, <a class="el" href="struct_x_qspi_psu.html#ae6039f5b4f8cdf2e528931ec383deb31">XQspiPsu::IsReady</a>, <a class="el" href="struct_x_qspi_psu.html#abcf49b02b0b90a7eecf9fb5ba40ac0b3">XQspiPsu::ReadMode</a>, <a class="el" href="group__qspipsu__v1__0.html#ga1d76a2f706f3988da79345132e484303">XQSPIPSU_CFG_OFFSET</a>, and <a class="el" href="group__qspipsu__v1__0.html#gab88bcdb0f53b21b79cd0805cfd14cb89">XQspiPsu_ReadReg</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga02ea5e95c8939c2be78d26c255a6ba6f">&#9670;&nbsp;</a></span>XQspiPsu_SetStatusHandler()</h2>

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          <td class="memname">void XQspiPsu_SetStatusHandler </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>CallBackRef</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__qspipsu__v1__0.html#ga6af4d9d05fc91cdef8a59c46b026c3b6">XQspiPsu_StatusHandler</a>&#160;</td>
          <td class="paramname"><em>FuncPointer</em>&#160;</td>
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        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p><code>#include &lt;<a class="el" href="xqspipsu_8c.html">xqspipsu.c</a>&gt;</code></p>

<p>Sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to upper layer software. </p>
<p>The handler executes in an interrupt context, so it must minimize the amount of processing performed. One of the following status events is passed to the status handler.</p>
<pre></pre><pre>XST_SPI_TRANSFER_DONE           The requested data transfer is done</pre><pre>XST_SPI_TRANSMIT_UNDERRUN       As a slave device, the master clocked data
                        but there were none available in the transmit
                        register/FIFO. This typically means the slave
                        application did not issue a transfer request
                        fast enough, or the processor/driver could not
                        fill the transmit register/FIFO fast enough.</pre><pre>XST_SPI_RECEIVE_OVERRUN The QSPIPSU device lost data. Data was received
                        but the receive data register/FIFO was full.</pre><pre></pre> <dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_qspi_psu.html" title="The XQspiPsu driver instance data. ">XQspiPsu</a> instance. </td></tr>
    <tr><td class="paramname">CallBackRef</td><td>is the upper layer callback reference passed back when the callback function is invoked. </td></tr>
    <tr><td class="paramname">FuncPointer</td><td>is the pointer to the callback function.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd></dd></dl>
<p>The handler is called within interrupt context, so it should do its work quickly and queue potentially time-consuming work to a task-level thread. </p>

<p class="reference">References <a class="el" href="struct_x_qspi_psu.html#ae6039f5b4f8cdf2e528931ec383deb31">XQspiPsu::IsReady</a>, and <a class="el" href="struct_x_qspi_psu.html#aaf2ea17aa1aae667ccc6190222e218f7">XQspiPsu::StatusRef</a>.</p>

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<h2 class="groupheader">Variable Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#ga0a1440bbf114a2e065b65bca531a14c3">&#9670;&nbsp;</a></span>XQspiPsu_ConfigTable <span class="overload">[1/2]</span></h2>

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          <td class="memname"><a class="el" href="struct_x_qspi_psu___config.html">XQspiPsu_Config</a> XQspiPsu_ConfigTable[XPAR_XQSPIPSU_NUM_INSTANCES]</td>
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<p><code>#include &lt;<a class="el" href="xqspipsu__sinit_8c.html">xqspipsu_sinit.c</a>&gt;</code></p>

<p>This table contains configuration information for each QSPIPSU device in the system. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga0a1440bbf114a2e065b65bca531a14c3">&#9670;&nbsp;</a></span>XQspiPsu_ConfigTable <span class="overload">[2/2]</span></h2>

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          <td class="memname"><a class="el" href="struct_x_qspi_psu___config.html">XQspiPsu_Config</a> XQspiPsu_ConfigTable[XPAR_XQSPIPSU_NUM_INSTANCES]</td>
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<p><code>#include &lt;<a class="el" href="xqspipsu__g_8c.html">xqspipsu_g.c</a>&gt;</code></p>
<b>Initial value:</b><div class="fragment"><div class="line">= {</div><div class="line">        {</div><div class="line">                XPAR_XQSPIPSU_0_DEVICE_ID, </div><div class="line">                XPAR_XQSPIPSU_0_BASEADDR,  </div><div class="line">                XPAR_XQSPIPSU_0_QSPI_CLK_FREQ_HZ,</div><div class="line">                XPAR_XQSPIPSU_0_QSPI_MODE,</div><div class="line">                XPAR_XQSPIPSU_0_QSPI_BUS_WIDTH</div><div class="line">        },</div><div class="line">}</div></div><!-- fragment -->
<p>This table contains configuration information for each QSPIPSU device in the system. </p>

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